MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-49-Using-the-Zynq-SoC-s/ba-p/518579
OCMに対するerror protection
We can also add error protection to the OCM using the OCM Control Parity control register if we are using it for a particularly critical application. You can set odd or even parity individually on each of the 16 bytes that make up the 128-bit word stored at each OCM address. Through this register we can also configure how the Zynq SoC handles parity errors (by issuing the OCM shared interrupt (number 35) or by sending an AXI read error (SLVERR) when a read error is detected, for example).
Table 7-3: PS and PL Shared Peripheral Interrupt (SPI)の一部
| Source | Interrupt Name | IRQ ID# | Status Bits | Required Type |
|---|---|---|---|---|
| CPU 1, 0 | 33:32 | spi_status_0[1:0] | Rising edge | |
| APU | L2 Cache | 34 | spi_status_0[2] | High level |
| OCM | 35 | spi_status_0[3] | High level |