Several interrupt generation sources are configurable:
- Level-sensitive (high/low)
- Rising/falling edge
- Asynchronous rising/falling edge
レベルで検知。エッジで検知。まではわかる。
非同期のエッジ検知というのは初めて出くわした。
At the system clock frequency, the pin is sampled with the criteria for generation of an interrupt being a stable transition within a 3-cycle window, i.e. a record of "1 0 0" or "0 1 1". Asynchronous detection bypasses this synchronisation to enable the detection of very narrow events.
3 cycleでなく1 0や0 1だけで検知ということだろうか。