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@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-SoC-s-Private-Watchdog-Adam-Taylor-s-MicroZed/ba-p/405273
Each of the two ARM Cortex-A9 processors within the Zynq SoC has a private watchdog timer. These private watchdogs can be used as either a timer like the private timer (discussed in the previous blog post in this series) or as a watchdog.
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The Zynq watchdog timer is controlled via six registers:
- Watchdog Load Register: Holds the value which the watchdog timer counts down from. In auto-reload mode, the watchdog counter resets to the value stored in this register. Writes to this register will result in the watchdog counter register being reset to this value.
- Watchdog Counter Register: This is the watchdog counter itself. It’s decrementing counter. Depending upon the watchdog mode, writing to this register reloads the counter. In watchdog mode, this register can only be updated by writing to the Watchdog Load Register.
- Watchdog Control Register: This register controls the configuration of the watchdog (timer or watchdog), the pre-scaler setting, the interrupt enable, auto-reload mode, and the enabling of the watchdog in its currently configured mode.
- Watchdog Interrupt Status Register: Contains a single event flag that shows when the counter has reached zero. Writing to this register resets it.
- Watchdog Reset Status Register: This register contains a single bit that is only cleared by power-on reset (not a watchdog-triggered reset). It can also be cleared by a software application. The reset status bit allows the software to determine whether or not the reason for a reboot was caused by a watchdog timeout.
- Watchdog Disable Register: This register requires two specific patterns to be written to it to enable the watchdog mode bit within the Watchdog Control Register when the watchdog is set to timer mode.