@ Adam Taylor blog
The Zynq SoC’s PL is programmed via the Processor Configuration Access Port (PCAP), which allows both partial and full PL configuration. (If you’d like more detailed information about the Zynq SoC’s PCAP, see “Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices”)
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The PS can also read back the PL configuration and check for errors, which can be very handy if you are using the Zynq SoC in an environment where it may be subject to single-event functional interrupts (SEFI).