Zybo > Chronicles blog 51 > AMPの使用 > 7. OCMによるCore同士の通信 > 割込みの使用 > SW_INT_ID定義 / GICのConnect

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@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-51-Interrupts-and-AMP/ba-p/525489

Core0, Core1間でのOCM経由でのデータ受渡しに関してInterruptを使う。

Each ARM Cortex-A9 processor core in the Zynq SoC has 16 software-generated interrupts.

…

For this example, we will use Core 0 to generate an interrupt that informs Core 1 that there has been an updated LED pattern received.

16のうちの１つを使用するため以下を定義し、Core0, Core1のソフトで共用する。

# define SW_INT_ID                   0

The next thing we need to do within Core 1—the core receiving the interrupt—is to connect the software-generated interrupt to the GIC (generic interrupt controller) and then enable the interrupt.

Connecting the interrupt is achieved by using the function XScuGIC_Connect.

Status = XScuGic_Connect(GicInstancePtr, SW_INT_ID,
         (Xil_ExceptionHandler)sgi_handler, (void *)GicInstancePtr);
if (Status != XST_SUCCESS) {
    print("error setting SGI");
    return XST_FAILURE;
}
XScuGic_Enable(GicInstancePtr, SW_INT_ID);