Zybo > Chronicles blog 27 > -0.0088x2 + 1.7673x + 131.29 のVHDL実装 / XSDKでの使用

MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-Seven-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/438888

http://qiita.com/7of9/items/7d4394b9a05ed7b97e6f
の計算の実装

Having calculated the above we are ready to implement the design within the Vivado peripheral that we created in previous installments. The first implementation step is to open up the block diagram view within Vivado, right click on the peripheral, and select “Edit in IP Packager”. Once the IP Packager opens within the top-level file, we can easily implement a simple process that performs the calculation over a number of clock cycles. (Five clocks in this example, although you could optimize this further.)

.vhd

PROCESS(s00_axi_aclk)
BEGIN
    IF rising_edge(s00_axi_aclk) THEN
      squared <= signed( '0' & reg1(15 DOWNTO 0)) * signed('0' & reg1(15 DOWNTO 0));
      cx2 <= (squared * c);
      bx <= (signed('0' & reg1(15 DOWNTO 0)) * b);
      res_int <= a + cx2(48 DOWNTO 32) + ("000" & bx(32 DOWNTO 19));
      result(15 DOWNTO 0) <= std_logic_vector(res_int(res_int'high - 1 DOWNTO 0));
    END IF;
END PROCESS;

res_int'highという書き方は未消化。

XSDKでは以下のようにiをレジスタに書込んで、その結果を読込みしている。

for(i=0; i<2560; i = i+25 ){
      XScuTimer_LoadTimer(&Timer, TIMER_LOAD_VALUE);
      timer_start = XScuTimer_GetCounterValue(&Timer);
      XScuTimer_Start(&Timer);
      ADAMS_PERIHPERAL_mWriteReg(Adam_Low, 4, i);
      result = ADAMS_PERIHPERAL_mReadReg(Adam_Low, 12);
      XScuTimer_Stop(&Timer);
      timer_value = XScuTimer_GetCounterValue(&Timer);
      printf("%d,%lu,%lu,%lu, \n\r",i,result,timer_start, timer_value);
}