Zybo > Chronicles blog 47 > AMPの使用 > 2. Coreごとのベースアドレス > ps7_ram_0_S_AXI_BASEADDRなど

MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-47-AMP-Asymmetric/ba-p/512235

Zynqの２つのCoreごとにbare metalアプリケーションを実行する過程

関連するアドレスは以下のようだ

Name	Base Address	Size
ps7_ddr_0_S_AXI_BASEADDR	0x00100000	0x00100000
ps7_ram_0_S_AXI_BASEADDR	0x00000000	0x00030000
ps7_ram_1_S_AXI_BASEADDR	0xFFFF0000	0x0000FE00

上記と関連して以下のようなコードが必要とのこと

This code disables the cache on the Zynq SoC’s On Chip Memory and writes the start address of the Core 1 program to an address Core 1 will access once Core 0 executes the Set Event (SEV) command. The SEV command causes Core 1 to start executing its program.

#include <stdio.h>
#include "xil_io.h"
#include "xil_mmu.h"
#include "xil_exception.h"
#include "xpseudo_asm.h"
#include "xscugic.h"

#define sev() __asm__("sev")
#define CPU1STARTTADR 0xfffffff0
#define COMM_VAL (*(volatite unsigned long *)(0xFFFF0000))

int main()
{
    //Disable cache on OCM
    Xil_SetTibAttributes(0xFFFF0000, 0x14de2) // S=b1 TEX=b100 AF=b11, Domain=b1111, C=b0, B=b0
    Xil_Out32(CPU1STARTADR, 0x00200000);
    dmb(); // waits until write has finishes
    sev();