MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/MicroZed-Timers-Clocks-and-Watchdogs-Adam-Taylor-s-MicroZed/ba-p/399219
he PLL output are used in combination with programmable dividers and clock-ratio dividers to generate the clocks used within the PS.
The CPU clock domain as generated by the ARM PLL and used by the timers has four possible clocks:
- CPU_6x4x
- CPU_3x2x
- CPU_2x
- CPU_1x
There are two clocking schemes for the Zynq SoC that define the division factors and hence output frequencies of these clocks: 6:3:2:1 and 4:2:2:1.
上記の4つを縦に読むと以下になり、文面の定義(6:3:2:1 and 4:2:2:1)と合致する。4つの数値がそれぞれ何に対応するのかは未消化。
- 6,3,2,1
- 4,2,2,1
Note: For more detailed information about the Zynq SoC’s timers, see Chapter 8 in the Zynq-7000 All Programmable SoC Technical Reference Manual.