RTL記述とモデルベース記述で FPGA 設計をしている人です (もっぱら Verilog HDL、DSP Builder for Intel(R) FPGA、でほぼ Intel FPGA で動かしています)
Qiita Engineer Festa
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$ analyze @rtl_modeler
posted articles:
- FPGA:83%
- Simulink:67%
- DSP:50%
- モデルベース開発:50%
- DSP-Builder:50%
answered questions:
- No data