@ryo_i6

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京都市内で職が欲しい人。北区付近だと嬉しい。

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SystemVerilog Verilog Chisel FPGA HDL VHDL

$ analyze @ryo_i6

posted articles:

VHDL:71%
FPGA:29%
GHDL:24%
SystemVerilog:18%
Vunit:18%

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