はてなダイアリー to Markdown > v0.5 > Tex:表記対応
の続き
v0.1はこちら
code v0.6
- FPGAのVerilog-HDLコードとVHDLコードの記事がはてなダイアリーにあったため、対応した
...
def conv_super_pre_notation(astr):
astr = astr.replace(">||", "```")
astr = astr.replace(">|cpp|", "```cpp")
astr = astr.replace(">|c|", "```c")
astr = astr.replace("||<", "```")
astr = astr.replace(">|verilog|", "```verilog")
astr = astr.replace(">|vhdl|", "```vhdl")
return astr
...
全コード
import sys
import re
# on Python 3.5
'''
v0.6 Jun. 22, 2018
- conv_super_pre_notation() handles [vhdl]
- conv_super_pre_notation() handles [verilog]
v0.5 May, 29, 2018
- add conv_tex()
v0.4 Apr. 25, 2018
- add conv_tableFormat()
v0.3 Apr. 25, 2018
- conv_super_pre_notation() takes cpp notation
v0.2 Apr. 25, 2018
- add conv_super_pre_notation()
- add conv_sublist()
v0.1 Apr. 24, 2018
- sub list is converted to Markdown style
'''
def conv_tex(intxt):
if r"[Tex:" in intxt or r"[tex:" in intxt:
wrk = re.sub('\[Tex:', r'```math\r\n', intxt)
wrk = re.sub('\[tex:', r'```math\r\n', wrk)
wrk = re.sub(r']', r'\r\n```', wrk)
return wrk
return intxt
def conv_sublist(astr):
if "---" in astr:
astr = astr.replace("---", SPACE4 + SPACE4 + "-")
if "--" in astr:
astr = astr.replace("--", SPACE4 + "-")
return astr
def conv_super_pre_notation(astr):
astr = astr.replace(">||", "```")
astr = astr.replace(">|cpp|", "```cpp")
astr = astr.replace(">|c|", "```c")
astr = astr.replace("||<", "```")
astr = astr.replace(">|verilog|", "```verilog")
astr = astr.replace(">|vhdl|", "```vhdl")
return astr
def getTableFormat(numVertical):
wrk = "|"
for loop in range(numVertical - 1): # -1: except for first
wrk += ":-:|"
return wrk
def conv_tableFormat(astr):
global countTbl
if "|" in astr:
countTbl += 1
if countTbl == 2:
num = astr.count('|')
fmt = getTableFormat(num)
return fmt + "\r\n" + astr
else:
countTbl = 0
return astr
# read from stdin
lines = sys.stdin.readlines()
SPACE4 = " "
countTbl = 0 # Table format counter
for elem in lines:
wrk = conv_sublist(elem)
wrk = conv_super_pre_notation(wrk)
wrk = conv_tableFormat(wrk)
wrk = conv_tex(wrk)
print(wrk, end='')
問題点
VHDLのコードのコメント-- 2to4デコーダー
の--
は、はてなのリスト表記--
と被る。
v0.6までは--
はリストとして変換されてしまうので、あとで手直しが必要となる。